In the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of cells of the memory matrix. The reason for the high probability of defects of this type resides in the fact that in a semiconductor memory chip the greater part of the area is occupied by the matrix of memory cells itself.
In order to avoid that the presence of a limited number of defective memory cells on many millions force the rejection of the entire chip, the technique is known of providing for the manufacture of a certain number of additional memory cells, commonly called "redundancy cells", to be used as a replacement of those cells that, during testing of the integrated component, prove defective; the circuits, with which the integrated component must of necessity be provided, designed to operate the abovementioned functional replacement of a defective cell with a redundancy cell are indicated as a whole with the name of "redundancy circuits", while the set of redundancy cells and circuits are defined for short as "redundancy".
Since semiconductor memories are organized in matrix structures wherein the single memory cells are located at the intersection of rows (known as "word lines") and of columns (known as "bit lines") of the matrix itself, what takes place in practice is the replacement of those rows or of those columns containing defective cells with as many rows or columns of redundancy cells (known as "redundancy rows" and "redundancy columns", respectively), storing the configuration of address signals corresponding to each defective line or column in special non-volatile memory registers (for example, fuses, or programmable but non-erasable memory cells) so that whenever said combination of address signals shows up again at the input of the integrated component, the replacement is automatically executed and, instead of accessing the defective cells, access is gained to the redundancy cells that replace them.
A first embodiment of redundancy provides for the presence of groups of redundancy bit lines, where each of these groups is associated with a respective sector of the memory matrix, comprising a given number of bit lines of memory cells, constituting the portion of the memory matrix itself related to a data input/output line of the integrated component.
For the purposes of the selection of a particular bit line, each of the abovementioned sectors is generally in turn divided into packets of bit lines, say eight packets of eight bit lines each for a total of 64 bit lines in each sector.
The selection of a given bit line among the 64 bit lines constituting a sector is executed by means of a twin-level decoding of the address signals: one among eight signals known as being of the first level is triggered to select one among the eight bit lines of each packet, while the triggering of one among eight signals known as being of the second level allows the selection of one among the eight packets. Said first- and second-level signals generally drive transistors that are placed in series with the bit lines and that connect the latter to the reading circuit of the memory cells.
In this type of embodiment the selection of one of the redundancy bit lines is also executed by means of two levels of selection signals, where signals of the first level execute the selection of a redundancy bit line among those constituting one group, while a single second-level signal allows the connection of the group of redundancy bit lines to the reading circuit. The redundancy circuits proceed with the triggering of these first- and second-level signals related to the redundancy bit lines, and at the same time they inhibit the triggering of the signals for the selection of the bit line of the matrix containing the effective memory cell.
An architecture such as the one described poses some problems, however, in the design of the integrated circuit layout. In order to program the memory cells, in fact, with each of the abovementioned packets of matrix bit lines, as well as with the redundancy bit lines, there is associated a programming loading circuit, comprising a transistor that, depending on the data to be stored in the single memory cell, connects the bit line selected by the first-level signals to a programming voltage. Since the current required by the memory cell for its programming is generally fairly high, the size of said transistor is consequently fairly substantial. This circumstance does not present particular problems for transistors associated with packets of matrix bit lines, where the pitch between two of these transistors is, say, of eight bit lines; since, however, a group of redundancy bit lines is generally constituted by a smaller number of bit lines, the space available for the design of the corresponding programming transistor is restricted, and it is necessary to introduce irregularities in its size or in its design.
A second type of embodiment is known, wherein with the entire complex of the packets of matrix bit lines and of the group of redundancy bit lines there is associated a single loading circuit, of the type described earlier. It is evident that in this second type of architecture the problems that are found in the first type of architecture described do not exist, since the pitch between two successive programming transistors consists of many bit lines.
But in this case the programming transistor is no longer connected to the selected bit line through the first-level selection transistor only, but, rather, through the connection of the latter to the second-level selection transistor. This allows a limited regulation of the programming voltage across the drain of the memory cell to be programmed, due to the additional drop in voltage across the second-level selection transistor. Moreover, in order to limit this additional drop in voltage across the second-level selection transistor, it is necessary for the second-level selection signal to have a value that is higher than the programming voltage, with the consequent complication of the decoding circuits.
Lastly, since in order to speed up testing operations it is usual to program several bits simultaneously, the programming transistor must, in this second architecture, be able to drive a multiple number of bit lines simultaneously; this means that its size must be larger than that of a programming transistor for architectures of the type described earlier, and layout problems may arise.
In view of the described state of the prior art, the object of the present invention is to manufacture a semiconductor memory with a matrix architecture such that the abovementioned problems are avoided when providing redundant circuits or carrying out redundancy operations.